The present invention relates to semiconductor packages, and more particularly, to a semiconductor package using a lead frame as a chip carrier, which can reduce or minimize contact area between a chip and a die pad of the lead frame.
A lead-frame-based semiconductor package using a lead frame as a chip carrier usually renders a reliability issue in terms of thermal stresses being generated due to mismatch in CTE (coefficient of thermal expansion) between a chip and a silver paste for attaching the chip to the lead frame and between the silver paste and the lead frame. In particular, the chip is mounted on a die pad of the lead frame via the silver paste and encapsulated by an encapsulant; due to different CTEs (chip: about 4 ppm, silver paste: about 40 ppm, die pad: about 16 ppm), significant thermal stresses would be induced at interfaces between the chip and silver paste and between the silver paste and die pad, such that under temperature variation in a reliability test or practical operating environment, the semiconductor package may be subject to delamination and chip cracks by effect of thermal stresses, making quality of the semiconductor package undesirably degraded. This situation is more severe in the use of a larger die pad or chip in which contact area between the die pad and chip is increased and the die pad would suffer greater thermal stresses during a temperature cycle, thereby resulting in warpage and poor planarity of the die pad and further causing delamination between the chip and die pad.
In response to the above problems, a solution is to use a lead frame having a die pad being formed with an opening. As shown in FIG. 7, this lead frame 40 is composed of a die pad 400 and a plurality of leads 401, and the die pad 400 is formed with at least an opening 402 by which a chip 42 is mounted on the die pad 400 via an adhesive (not shown) and contact area between the chip 42 and die pad 400 can be reduced. However, although the chip 42 would be subject to less thermal stresses due to reduction in contact area between the chip 42 and die pad 400, this structure can only be applicable in the case of the chip 42 being larger in surface area than the opening 402 of the die pad 400, thereby setting a limitation to sizes and types of chips suitably used in the above structure. Moreover, fabrication of a die pad 400 in compliance with profile of the chip 42 increases process complexity and costs of the lead frame 40.
Accordingly, U.S. Pat. No. 5,455,454 discloses provision of a tape between a chip and a die pad of a lead frame. As shown in FIGS. 8A and 8B, this lead frame 50 is composed of a chip supporting structure including a plurality of supporting bars 502 and tie bars 503 that are integrally formed with the supporting bars 502 and connected to a frame (not shown) of the lead frame 50, and a plurality of leads 501 surrounding the chip supporting structure and connected to the frame. A tape 55 is attached to the chip supporting structure and has one surface thereof covering the supporting bars 502, part of the tie bars 503 and part of the leads 501, allowing a chip 52 to be mounted to an opposing surface of the tape 55.
Provision of the tape attached to the chip supporting structure for accommodating the chip can solve the problem of limitation in chip sizes, making the die pad not necessarily formed corresponding to profile of the chip. However, the use of the tape increases fabrication costs and difficulty in performing a die-bonding process for mounting the chip on the tape. Moreover, as the chip and tape are made of different materials, it may easily causes delamination at an interface between the chip and tape, and thus still fails to solve the problem of delamination between the chip and die pad.
A primary objective of the present invention is to provide a semiconductor package with a chip supporting member, which can prevent direct contact between a chip and a die pad to thereby eliminate chip cracks, delamination between the chip and die pad, and warpage of the die pad in response to thermal stresses, so as to assure reliability of the semiconductor package.
Another objective of the invention is to provide a semiconductor package with a chip supporting member, which allows variously sized or shaped chips to be accommodated by a single type of lead frame without having to fabricate a die pad in compliance with profile of the chips, so as to simplify fabrication processes for the lead frame and thereby reduce fabrication costs of the semiconductor package.
A further objective of the invention is to provide a semiconductor package with a chip supporting member for minimizing contact area between a chip and a die pad, so as to reduce undesirably effect from thermal stresses induced by CTE (coefficient of thermal expansion) mismatch between the chip and die pad on the semiconductor package.
In accordance of the foregoing and other objectives, the present invention proposes a semiconductor package with a chip supporting member, comprising: a lead frame having at least a die pad and a plurality of leads; a chip supporting member having a first surface and a second surface opposed to the first surface, wherein the second surface of the chip supporting member is attached to a central portion of the die pad, and positions on the first surface of the chip supporting member are spaced apart from corresponding positions on the second surface of the chip supporting member by an identical vertical distance; a chip mounted on the first surface of the chip supporting member, allowing the chip supporting member to be interposed between the chip and die pad; a plurality of bonding wires (such as gold wires) for electrically connecting the chip to the leads; and an encapsulant formed on the lead frame for encapsulating the chip supporting member, chip and bonding wires.
The chip supporting member can be made of a dummy die (i.e. functionless chip), a metal plate (such as copper, aluminum, etc.), or a polymer material having a CTE similar to that of the chip. Moreover, without affecting attachment between the chip and die pad, the chip supporting member can be flexibly shaped and sized. In order to prevent formation of voids during fabrication of the encapsulant, the chip support member has a height larger than a minimum distance capable of being penetrated by fillers of a resin used for forming the encapsulant. By disposing the chip supporting member between the chip and die pad, effect of thermal stresses induced by CTE mismatch on the chip and die pad can be reduced, thereby preventing delamination at e.g. comer portions thereof normally subjecting to relatively stronger thermal stresses so as to improve quality and reliability of the semiconductor package.